Semiconductor device and manufacturing method thereof

ABSTRACT

To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/609,925, filed Oct. 30, 2009, which claims the priority of JapanesePatent Application No. 2008-279865, filed Oct. 30, 2008, the contents ofwhich prior applications are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and amanufacturing method thereof, and, more particularly relates to asemiconductor device utilizing a planarizing process by CMP (ChemicalMechanical Polishing) and a manufacturing method thereof.

2. Description of Related Art

CMP is often used for planarizing a surface of respective layers inmanufacturing of semiconductor devices. In the planarizing process byCMP, dummy patterns for CMP (hereinafter called, “CMP dummy patterns” ormerely “dummy pattern(s)”) are arranged so as to avoid occurrence ofdishing and erosion (see Japanese Patent Application Laid-open No.2006-39587). Generally, the size, number, and arrangement of the CMPdummy patterns are determined to be optimized in the respective layerssubject to CMP.

Recently, however, as for more miniaturized semiconductor devices, thefollowing problems have been found when optical inspections areperformed to detect defects such as particles and short circuits ofpatterns.

That is, smaller defects and particles must be detected because ofminiaturizing of devices and thus the detection sensitivity needs to beincreased. When the detection sensitivity is increased, however, adifference between a dummy pattern in an upper layer and a dummy patternin a lower layer may appear as moire (interference fringe), because thedummy patterns are arranged to be optimized in the respective layers asdescribed above. Thus, in defect inspections, such moire may be detectedas a defect and defects caused by moire may be mixed with particles anddefects that should be detected originally, and all of them may bedetected as defects, resulting in an increased number of defects. On theother hand, when the detection sensitivity is decreased to preventgeneration of moire, minute particles and defects cannot be detected,causing a decrease in yield.

SUMMARY

The present invention seeks to solve one or more of the above problems,or to improve upon those problems at least in part.

In one embodiment, there is provided a semiconductor device thatincludes: a first layer provided above a semiconductor substrate andincluding a first wiring pattern planarized by CMP (Chemical MechanicalPolishing) and a plurality of first dummy patterns made of a samematerial as the first wiring pattern; and a second layer provided abovethe semiconductor substrate and including a second wiring patternplanarized by CMP and a plurality of second dummy patterns made of asame material as the second wiring pattern, wherein a central axis ofeach of the second dummy patterns coincides with that of a correspondingone of the first dummy patterns in a direction perpendicular to thesemiconductor substrate.

In another embodiment, there is provided a manufacturing method of asemiconductor device that includes: forming a first layer and a secondlayer to be planarized by first and second CMPs on a semiconductorsubstrate; and prior to forming the first and second layers, determiningnumber and arrangement of first dummy patterns for the first CMP formedin the first layer; and determining number and arrangement of seconddummy patterns for the second CMP formed in the second layer so that acentral axis of the second dummy pattern coincides with a central axisof the first dummy pattern in a direction perpendicular to thesemiconductor substrate.

According to the present invention, the central axis of the first dummypattern provided in the first layer coincides with that of the seconddummy pattern provided in the second layer in a direction perpendicularto the semiconductor substrate. Thus, when defects are opticallydetected, moire due to dummy patterns can be suppressed even if thedetection sensitivity is increased. Alternatively, even if the moire dueto dummy patterns is generated, that moire has regularity and can bedetermined as one due to dummy patterns. Therefore, minute particles anddefects can be correctly detected and thus the yield can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a flowchart for explaining a manufacturing method of asemiconductor device according to the present invention;

FIGS. 2A and 2B are diagrams for explaining a configuration of asemiconductor device 100 according to a first embodiment of the presentinvention;

FIG. 3 is a flowchart for explaining the manufacturing method of thesemiconductor device 100 according to the first embodiment;

FIGS. 4A and 4B are diagrams for explaining a configuration of asemiconductor device 100 m according to a modified example of the firstembodiment;

FIGS. 5A and 5B are diagrams for explaining a configuration of asemiconductor device 200 according to a second embodiment;

FIG. 6 is a flowchart for explaining the manufacturing method of thesemiconductor device 200 according to the second embodiment;

FIGS. 7A and 7B are diagrams for explaining a semiconductor device 300according to a third embodiment;

FIG. 8 is a flowchart for explaining the manufacturing method of thesemiconductor device 300 according to the third embodiment;

FIGS. 9A and 9B are diagrams for explaining a configuration of asemiconductor device 400 according to a fourth embodiment;

FIG. 10 is a flowchart for explaining the manufacturing method of thesemiconductor device 400 according to the fourth embodiment; and

FIGS. 11A and 11B are diagrams for explaining a configuration of asemiconductor device 500 according to a fifth embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

First, steps of forming dummy patterns in a manufacturing method of asemiconductor device according to the present invention is conceptuallydescribed with reference to a flowchart shown in FIG. 1.

As shown in FIG. 1, dummy pattern formable regions in the respectivelayers are extracted first (step S1001). It is then determined whetherthere exists any layer that dummy patterns should be close-packed (stepS1002). When the layer (indicated by X) that dummy patterns should beclose-packed exists (Yes), the number and arrangement of the dummypatterns are determined so that the dummy patterns are close-packed inthe layer X (step S1003). On the other hand, when the layer that dummypatterns should be close-packed does not exist (No), a layer with a highpriority set in advance is determined as the layer X and the number andarrangement of the dummy patterns are determined so that the dummypatterns are close-packed (step S1004). Next, whether a layer Y that thecentral axis of a dummy pattern needs to be coincided with that of thedummy pattern in the layer X exists is determined (step S1005). When thelayer Y exists that needs to be coincided (Yes), the part of the dummypattern formable region in the layer Y overlaps with the dummy patternformable region in the layer X is extracted (step S1006). On the otherhand, when the layer Y that the central axis of the dummy pattern needsto be coincided with that of the dummy pattern in the layer X does notexist (No), the number and arrangement of the dummy patterns aredetermined in the respective layers independently without consideringthe relationship between upper and lower layers (step S1007), and thesteps of forming dummy patterns end.

Subsequent to step S1006, the number and arrangement of the dummypatterns are determined in the extracted dummy pattern formable regionin the layer Y so that the dummy pattern is similar to the one in thelayer X and its central axis coincides with that of the one in the layerX (step S1008). Next, whether there remains any part that the dummypatterns can be arranged in the dummy pattern formable regions in therespective layers is determined (step S1009). When such a part does notremain (No), the steps of forming dummy patterns end. When such a partremains (Yes), the number and arrangement of the dummy patterns aredetermined in the respective layers independently without consideringthe relationship between the upper and lower layers (step S1010). StepsS1009 and S1010 are repeated until there is no part where the dummypatterns can be arranged, and the steps of forming dummy patterns endwhen the part where the dummy patterns can be arranged is not provided.

Preferred embodiments of the present invention will be explained belowin detail with reference to the accompanying drawings.

FIGS. 2A and 2B are explanatory diagrams of a configuration of asemiconductor device 100 according to a first embodiment of the presentinvention, where FIG. 2A is a schematic cross-sectional view and FIG. 2Bis a plan view as the semiconductor device 100 is viewed from its topsurface. For simplicity, only wiring patterns and CMP dummy patterns areshown in FIG. 2A and a semiconductor substrate, interlayer dielectricfilms or the like are omitted, and only the dummy patterns are shown inFIG. 2B.

As shown in FIGS. 2A and 2B, the semiconductor device 100 according tothe first embodiment includes a first layer 101 that is provided on asemiconductor substrate (not shown) and includes a first wiring pattern101 w planarized by CMP and a plurality of first dummy patterns 101 dmade of the same material as the first wiring pattern 101 w, a secondlayer 102 that is provided on the first layer 101 on the semiconductorsubstrate and includes a second wiring pattern 102 w planarized by CMPand a plurality of second dummy patterns 102 d made of the same materialas the second wiring pattern 102 w, and a third layer 103 that isprovided on the second layer 102 above the semiconductor substrate andincludes a third wiring pattern 103 w planarized by CMP and a pluralityof third dummy patterns 103 d made of the same material as the thirdwiring pattern 103 w.

Regions the wiring patterns 101 w to 103 w are not formed in therespective layers 101 to 103 become dummy pattern formable region 10Aand 10B and the dummy patterns 101 d to 103 d are arranged in therespective dummy pattern formable regions. According to the firstembodiment, the first dummy patterns 101 d are arranged to beclose-packed in the dummy pattern formable region 10A in the first layer101. The second dummy patterns 102 d are arranged in the dummy patternformable region 10A so that central axes thereof coincide with those ofcorresponding ones of the first dummy patterns 101 d in a directionperpendicular to the semiconductor substrate as shown by dashed lines.Similarly, the third dummy patterns 103 d are arranged so that centralaxes thereof coincide with those of corresponding ones of the firstdummy patterns 101 d in a direction perpendicular to the semiconductorsubstrate.

Because the first dummy pattern 101 d is not formed in the dummy patternformable region 10B, the second dummy patterns 102 d are arranged to beclose-packed in the region 10B. The third dummy patterns 103 d arearranged in the dummy pattern formable region 10B so that central axesthereof coincide with those of corresponding ones of the second dummypatterns 102 d in a direction perpendicular to the semiconductorsubstrate.

By having such a configuration, when the dummy patterns 101 d to 103 dare superimposed on each other (correspond to each other), central axesthereof always coincide with each other as shown in FIG. 2B. Thus, evenif the detection sensitivity is increased when defects are opticallydetected, generation of moire due to dummy patterns can be prevented.Accordingly, minute particles and defects can be correctly detected, andthus the yield can be improved.

A manufacturing method of the semiconductor device 100 according to thefirst embodiment is described next with reference to FIGS. 2A, 2B, and3.

FIG. 3 is a flowchart for explaining the manufacturing method of thesemiconductor device 100 according to the first embodiment, and showsprocesses for determining the number and arrangement of the dummypatterns 101 d to 103 d in the first to third layers 101 to 103 beforethe layers are formed in the semiconductor device 100 shown in FIGS. 2Aand 2B.

The dummy pattern formable regions 10A and 10B are extracted first (stepS11). The number and arrangement of the first dummy patterns 101 d arethen determined so that the first dummy patterns 101 d are close-packedin the dummy pattern formable region 10A including the first layer 101which should have a close-pack structure (step S12). The number andarrangement of the second dummy patterns 102 d are then determined basedon the arrangement of the first dummy patterns 101 d so that the centralaxes of the second dummy patterns 102 d formed in the second layer 102coincide with those of the first dummy patterns 101 d, respectively, ina direction perpendicular to the semiconductor substrate (step S13).Further, the number and arrangement of the third dummy patterns 103 dare determined based on the arrangement of the first dummy patterns 101d so that the central axes of the third dummy patterns 103 d formed inthe third layer 103 coincide with those of the first dummy patterns 101d, respectively, in a direction perpendicular to the semiconductorsubstrate (step S14). That is, as shown by arrows in the region 10A inFIG. 2A, when the positions (central axes) of the first dummy patterns101 d can be copied in the second layer 102 and the second dummypatterns 102 d can be placed at the copied positions, the second dummypatterns 102 d are arranged. Similarly, when the positions (centralaxes) of the first dummy patterns 101 d can be copied in the third layer103 and the third dummy patterns 103 d can be placed at the copiedpositions, the third dummy patterns 103 d are arranged.

Next, the number and arrangement of the second dummy patterns 102 d aredetermined in the dummy pattern formable region 10B so that the seconddummy patterns 102 d are close-packed (step S15). The number andarrangement of the third dummy patterns 103 d are then determined basedon the arrangement of the second dummy patterns 102 d so that thecentral axes of the third dummy patterns 103 d formed in the third layer103 coincide with those of the second dummy patterns 102 d,respectively, in a direction perpendicular to the semiconductorsubstrate (step S16). While the second layer has a close-pack structure,if the flatness of the third layer is highly required as compared to thesecond layer, the third layer can have a close-pack structure and thenumber and arrangement of the second dummy pattern 102 d in the secondlayer 102 can be determined based on the third layer.

Finally, because the third dummy pattern 103 d can be formed in theremaining dummy pattern formable region 10Br, the third dummy pattern103 d is additionally formed (step S17).

The number and arrangement of the dummy patterns formed in therespective layers are determined as described above. While the planarconfigurations of the dummy patterns formed in the respective layershave the same size in the first embodiment, the sizes of the dummypatterns in the respective layers can be set appropriately in therespective layers according to design standards. Such an example isshown in FIGS. 4A and 4B.

FIGS. 4A and 4B are explanatory diagrams of a configuration of asemiconductor device 100 m according to a modified example of the firstembodiment, where FIG. 4A is a schematic cross-sectional view and FIG.4B is a plan view as the semiconductor device 100 m is viewed from itstop surface. For simplicity, only wiring patterns and CMP dummy patternsare shown in FIG. 4A and a semiconductor substrate, interlayerdielectric films or the like are omitted, and FIG. 4B shows only thedummy patterns. Constituent elements in FIGS. 4A and 4B that are thesame as the ones shown in FIGS. 2A and 2B are denoted by like referencenumerals and descriptions thereof will be omitted.

As shown in FIGS. 4A and 4B, first dummy patterns 101 md in a firstlayer 101 m, second dummy patterns 102 md in a second layer 102 m, andthird dummy patterns 103 md in a third layer 103 m have different planesizes and are squares with different sizes in the semiconductor device100 m. Therefore, the first to third dummy patterns 101 md to 103 md arearranged in the dummy pattern formable region 10A so that central axesthereof coincide with each other. The second and third dummy patterns102 md and 103 md are arranged in the dummy pattern formable region 10Bso that central axes thereof coincide with each other like thesemiconductor device 100. According to the plan view, however, unlikeFIG. 2B, the patterns are not superimposed so as to be coincideperfectly with each other. Instead, the patterns with different sizesare superimposed so as to have the same central axis as shown in FIG.4B.

The planar configuration of the dummy pattern is not limited to squareand can be rectangular and even a polygon. Note that dummy patterns inupper and lower layers are preferably similar to each other. When thecentral axes of the dummy patterns in the upper and lower layerscoincide with each other, while the size of the dummy pattern in theupper layer is different from that of the dummy pattern in the lowerlayer, differences between the upper and lower patterns whensuperimposed on each other (for example, differences in vertical andhorizontal directions) preferably coincide with each other. The squarepattern enables the dummy pattern to be packed efficiently, that is, tobe close-packed. Thus, the density within a chip can be corrected withhigh precision and dishing and erosion, which are characteristic to CMP,can be suppressed more efficiently.

According to the semiconductor device 100 m with such a configuration,when the dummy patterns 101 md to 103 md are superimposed on each other,central axes thereof always coincide with each other like thesemiconductor device 100. Thus, even if the detection sensitivity isincreased when defects are optically detected, generation of moire dueto dummy patterns can be suppressed.

Because the manufacturing method of the semiconductor device 100 m shownin FIGS. 4A and 4B is the same as that of the semiconductor device 100,descriptions thereof will be omitted.

While a case that the first dummy patterns 101 d (101 md) formed in thefirst layer 101 (101 m) are close-packed is described as an example inthe first embodiment, a layer which should have a close-pack structureis different for design standards of devices. Dummy patterns in thebottom layer do not need to be always close-packed. A layer whoseflatness is required in the strictest sense in terms of device's designmanagement is determined to have a close-pack structure. Accordingly, asecond embodiment of the present invention describes a case that thesecond layer has a close-pack structure with reference to FIGS. 5A, 5B,and 6.

FIGS. 5A and 5B are explanatory diagrams of a configuration of asemiconductor device 200 according to the second embodiment, where FIG.5A is a schematic cross-sectional view and FIG. 5B is a plan view as thesemiconductor device 200 is viewed from its top surface. For simplicity,only wiring patterns and CMP dummy patterns are shown in FIG. 5A and asemiconductor substrate, interlayer dielectric films or the like areomitted, and FIG. 5B shows only the dummy patterns.

As shown in FIGS. 5A and 5B, the semiconductor device 200 according tothe second embodiment includes a first layer 201 that is provided on asemiconductor substrate (not shown) and includes a first wiring pattern201 w planarized by CMP and a plurality of first dummy patterns 201 dmade of the same material as the first wiring pattern 201 w, a secondlayer 202 that is provided on the first layer 201 on the semiconductorsubstrate and includes a second wiring pattern 202 w planarized by CMPand a plurality of second dummy patterns 202 d made of the same materialas the second wiring pattern 202 w, and a third layer 203 that isprovided on the second layer 202 above the semiconductor substrate andincludes a third wiring pattern 203 w planarized by CMP and a pluralityof third dummy patterns 203 d made of the same material as the thirdwiring pattern 203 w.

Regions the wiring patterns 201 w to 203 w are not formed in therespective layers 201 to 203 become dummy pattern formable regions 20Aand 20B and the dummy patterns 201 d to 203 d are arranged in therespective regions. According to the second embodiment, the second dummypatterns 202 d are arranged to be close-packed in the dummy patternformable regions 20A and 20B in the second layer 202. The first dummypatterns 201 d are arranged in the dummy pattern formable region 20A sothat central axes thereof coincide with those of corresponding ones ofthe second dummy patterns 202 d in a direction perpendicular to thesemiconductor substrate. Similarly, the third dummy patterns 203 d arearranged so that central axes thereof coincide with those ofcorresponding ones of the second dummy patterns 202 d in a directionperpendicular to the semiconductor substrate.

By having such a configuration, when the dummy patterns 201 d to 203 dare arranged to be superimposed on each other, central axes thereofalways coincide with each other as shown in FIG. 5B. Therefore, thesecond embodiment can achieve identical effects as those of the firstembodiment.

A manufacturing method of the semiconductor device 200 according to thesecond embodiment is described next with reference to FIGS. 5A, 5B, and6.

FIG. 6 is a flowchart for explaining the manufacturing method of thesemiconductor device 200 according to the second embodiment, and showsprocesses for determining the number and arrangement of the dummypatterns 201 d to 203 d in the first to third layers 201 to 203 beforethe layers are formed in the semiconductor device 200 shown in FIGS. 5Aand 5B.

The dummy pattern formable regions 20A and 20B are extracted first (stepS21). The number and arrangement of the second dummy patterns 202 d arethen determined so that the second dummy patterns 202 d are close-packedin the dummy pattern formable regions 20A and 20B including the secondlayer 202 which should have a close-pack structure (step S22). Thenumber and arrangement of the first dummy patterns 201 d are determinedbased on the arrangement of the second dummy patterns 202 d so that thecentral axes of the first dummy patterns 201 d formed in the first layer201 coincide with that of the second dummy patterns 202 d, respectively,in a direction perpendicular to the semiconductor substrate (step S23).Further, the number and arrangement of the third dummy patterns 203 dare determined based on the arrangement of the second dummy patterns 202d so that the central axes of the third dummy patterns 203 d formed inthe third layer 203 coincide with those of the second dummy patterns 202d, respectively, in a direction perpendicular to the semiconductorsubstrate (step S24). That is, as shown by arrows in the region 20A inFIG. 5A, when the positions (central axes) of the second dummy patterns202 d can be copied in the first layer 201 and the first dummy patterns201 d can be placed at the copied positions, the first dummy patterns201 d are arranged. Similarly, as shown by arrows in the regions 20A and20B in FIG. 5A, when the positions (central axes) of the second dummypatterns 202 d can be copied in the third layer 203 and the third dummypatterns 203 d can be placed at the copied positions, the third dummypatterns 203 d are arranged.

Because the third dummy pattern 203 d can be formed in the remainingdummy pattern formable region 20Br, the third dummy pattern 203 d isadditionally formed (step S25).

While a case that the CMP dummy pattern is formed in the wiring layer inwhich the wiring pattern is formed has been described in the first andsecond embodiments, the CMP dummy pattern does not need to be formedonly in the wiring layer. A third embodiment of the present inventiondescribes a case that the CMP dummy pattern is provided in an STI(Shallow Trench Isolation) region as an element isolation regionprovided in a semiconductor substrate.

FIGS. 7A and 7B are explanatory diagram of a semiconductor device 300according to the third embodiment, where FIG. 7A is a schematiccross-sectional view and FIG. 7B is a plan view as the semiconductordevice 300 is viewed from its top surface. For simplicity, interlayerdielectric films or the like are omitted in FIG. 7A, and FIG. 7B showsonly dummy patterns.

As shown in FIGS. 7A and 7B, the semiconductor device 300 according tothe third embodiment includes a first layer 301 that is provided on asemiconductor substrate 303 and includes a first wiring pattern 301 wplanarized by CMP and a plurality of first dummy patterns 301 d made ofthe same material as the first wiring pattern 301 w, a second layer 302that is provided on the first layer 301 on the semiconductor substrateand includes a second wiring pattern 302 w planarized by CMP and aplurality of second dummy patterns 302 d made of the same material asthe second wiring pattern 302 w, and a plurality of third dummy patterns303 d each of which is formed of a wide STI region 303 t in an elementisolation region 303 i of the semiconductor substrate 303 and a part ofthe semiconductor substrate 303 in the STI region 303 t.

Regions where the wiring patterns 301 w and 302 w are not formed in thefirst and second layers 301 and 302 become dummy pattern formableregions 30A and 30B. The interior portion of the wide STI region 303 tin the semiconductor substrate 303 becomes the dummy pattern formableregion 30A. The dummy patterns 301 d to 303 d are arranged in therespective regions. According to the third embodiment, the first dummypatterns 301 d are arranged to be close-packed in the dummy patternformable region 30A in the first layer 301. The second dummy patterns302 d are arranged in the dummy pattern formable region 30A so thatcentral axes thereof coincide with those of corresponding ones of thefirst dummy patterns 301 d in a direction perpendicular to thesemiconductor substrate 303 as shown by dashed lines. Similarly, thethird dummy patterns 303 d are arranged so that central axes thereofcoincide with those of corresponding ones of the first dummy pattern 301d in a direction perpendicular to the semiconductor substrate 303.

Because the first dummy pattern 301 d is not formed in the dummy patternformable region 30B, the second dummy patterns 302 d are arranged to beclose-packed in this region.

Not only the dummy patterns 301 d and 302 d provided in the respectivewiring layers but also the dummy patterns 303 d provided in thesemiconductor substrate 303 have the same central axis when superimposedon each other in the third embodiment as shown in FIG. 7B. Therefore,the third embodiment can also achieve effects identical to those of thefirst and second embodiments.

A manufacturing method of the semiconductor device 300 according to thethird embodiment is described next with reference to FIGS. 7A, 7B, and8.

FIG. 8 is a flowchart for explaining the manufacturing method of thesemiconductor device 300 according to the third embodiment, and showsprocesses for determining the number and arrangement of the dummypatterns 301 d to 303 d in the element isolation region 303 i and firstand second layers 301 and 302 before the element isolation region andthe respective layers are formed in the semiconductor device 300 shownin FIGS. 7A and 7B.

The dummy pattern formable regions 30A and 30B are extracted first (stepS31). Next, the number and arrangement of the first dummy patterns 301 dare determined in the dummy pattern formable region 30A including thefirst layer 301 which should have a close-pack structure so that thefirst dummy patterns 301 d are close-packed (step S32). The number andarrangement of the second dummy patterns 302 d are then determined basedon the arrangement of the first dummy patterns 301 d so that the centralaxes of the second dummy patterns 302 d formed in the second layer 302coincide with that of the first dummy patterns 301 d, respectively, in adirection perpendicular to the semiconductor substrate 303 (step S33).The number and arrangement of the third dummy patterns 303 d are thendetermined based on the arrangement of the first dummy patterns 301 d sothat the central axes of the third dummy patterns 303 d formed in thesemiconductor substrate 303 coincide with that of the first dummypatterns 301 d, respectively, in a direction perpendicular to thesemiconductor substrate 303 (step S34). That is, as shown by arrows inthe region 30A in FIG. 7A, when the positions (central axes) of thefirst dummy patterns 301 d can be copied in the second layer 302 and thesecond dummy patterns 302 d can be placed at the copied positions, thesecond dummy patterns are arranged. Similarly, when the positions(central axes) of the first dummy patterns 301 d can be copied in thesemiconductor substrate 303 and the third dummy patterns 303 d can beplaced at the copied positions, respectively, the third dummy patternsare arranged.

Finally, the number and arrangement of the second dummy patterns 302 dare determined in the dummy pattern formable region 30B so that thesecond dummy patterns are close-packed (step S35).

Next, a fourth embodiment of the present invention describes a case thatan impermeable film is provided on a semiconductor substrate withreference to FIGS. 9A, 9B, and 10.

FIGS. 9A and 9B are explanatory diagram of a configuration of asemiconductor device 400 according to the fourth embodiment, where FIG.9A is a schematic cross-sectional view and FIG. 9B is a plan view as thesemiconductor device 400 is viewed from its top surface. For simplicity,only wiring patterns and CMP dummy patterns are shown in FIG. 9A and asemiconductor substrate, interlayer dielectric films or the like areomitted, and FIG. 9B shows only the dummy patterns.

As shown in FIGS. 9A and 9B, the semiconductor device 400 according tothe fourth embodiment includes a first layer 401 that is provided on asemiconductor substrate (not shown) and includes a first wiring pattern401 w planarized by CMP and a plurality of first dummy patterns 401 dmade of the same material as the first wiring pattern 401 w, a secondlayer 402 that is provided on the first layer 401 on the semiconductorsubstrate and includes a second wiring pattern 402 w planarized by CMPand a plurality of second dummy patterns 402 d made of the same materialas the second wiring pattern 402 w, a third layer 403 that is providedbetween the semiconductor substrate and the first layer and includes athird wiring pattern 403 w planarized by CMP and a plurality of thirddummy patterns 403 d made of the same material as the third wiringpattern 403 w, and an impermeable film 410 between the third layer 403and the first layer 401. Examples of the impermeable film 410 includeamorphous carbon used as insulation films and metallic films used asplate electrodes for capacitors.

Regions where the wiring patterns 401 w to 403 w are not formed in therespective layers 401 to 403 become dummy pattern formable regions 40Aand 40B and the dummy patterns 401 d to 403 d are arranged in therespective regions. According to the fourth embodiment, the first dummypatterns 401 d are arranged to be close-packed in the dummy patternformable regions 40A and 40B in the first layer 401. The second dummypatterns 402 d are arranged in the dummy pattern formable regions 40Aand 40B so that central axes thereof coincide with those ofcorresponding ones of the first dummy patterns 401 d in a directionperpendicular to the semiconductor substrate as shown by dashed lines.

Meanwhile, in the third layer 403 below the impermeable film 410, thethird dummy patterns 403 d are arranged to be close-packed in the dummypattern formable region 40A not based on the arrangement of the firstand second dummy patterns 401 d and 402 d. This is because the dummypatterns below the impermeable film 410 do not affect results of opticaldefect inspection since inspection light does not transmit through theimpermeable film 410. Thus, the number and arrangement of the thirddummy patterns 403 d in the third layer 403 can be determined regardlessof the first and second dummy patterns 401 d and 402 d.

Therefore, as shown in FIG. 9B, when the first dummy pattern 401 d andthe second dummy pattern 402 d are arranged to be superimposed on eachother, central axes thereof always coincide with each other. The thirddummy pattern 403 d is arranged so that central axis thereof is shiftedfrom that of a corresponding one of the first dummy pattern 401 d (whenthe third dummy pattern 403 d is superimposed at least partially on thedummy pattern 401 d) in a direction perpendicular to the semiconductorsubstrate. By having such a configuration, generation of moire due todummy patterns can be prevented when defects are optically detected andthe dummy patterns can be arranged in the layer below the impermeablefilm 410 so that flatness by CMP is more improved.

A manufacturing method of the semiconductor device 400 according to thefourth embodiment is described next with reference to FIGS. 9A, 9B, and10.

FIG. 10 is a flowchart for explaining the manufacturing method of thesemiconductor device 400 according to the fourth embodiment, and showsprocesses for determining the number and arrangement of the dummypatterns 401 d to 403 d in the first to third layers 401 to 403 beforethe layers are formed in the semiconductor device 400 shown in FIGS. 9Aand 9B.

The dummy pattern formable regions 40A and 40B are extracted first (stepS41). The number and arrangement of the first dummy patterns 401 d arethen determined in the dummy pattern formable regions 40A and 40B in thefirst layer 401 which should have a close-pack structure so that thefirst dummy patterns 401 d are close-packed (step S42). The number andarrangement of the second dummy patterns 402 d are then determined basedon the arrangement of the first dummy patterns 401 d so that the centralaxes of the second dummy patterns 402 d formed in the second layer 402coincide with those of the first dummy patterns 401 d, respectively, ina direction perpendicular to the semiconductor substrate (step S43). Thenumber and arrangement of the third dummy patterns 403 d are thendetermined in the dummy pattern formable region 40A in the third layerso that the third dummy patterns 403 d are close-packed (step S44).

Finally, because the second dummy pattern 402 d can be formed in theremaining dummy pattern formable region 40Br, the second dummy pattern402 d is additionally formed (step S45) in the region.

While the central axes of the dummy patterns in the respective layerscoincide with each other in the first to fourth embodiments, centralaxes thereof do not need to coincide with each other. Next, a fifthembodiment of the present invention describes a semiconductor deviceincluding dummy patterns whose central axes do not coincide with eachother.

FIGS. 11A and 11B are explanatory diagram of a configuration of asemiconductor device 500 according to the fifth embodiment, where FIG.11A is a schematic cross-sectional view and FIG. 11B is a plan view asthe semiconductor device 500 is viewed from its top surface. Forsimplicity, only wiring patterns and CMP dummy patterns are shown inFIG. 11A and a semiconductor substrate, interlayer dielectric films orthe like are omitted, and FIG. 11B shows only the dummy patterns.

As shown in FIGS. 11A and 11B, the semiconductor device 500 according tothe fifth embodiment includes a first layer 501 that is provided on asemiconductor substrate (not shown) and includes a first wiring pattern501 w planarized by CMP and a plurality of first dummy patterns 501 dmade of the same material as the first wiring pattern 501 w, a secondlayer 502 that is provided on the first layer 501 on the semiconductorsubstrate and includes a second wiring pattern 502 w planarized by CMPand a plurality of second dummy patterns 502 d made of the same materialas the second wiring pattern 502 w, and a third layer 503 that isprovided on the second layer 502 above the semiconductor substrate andincludes a third wiring pattern 503 w planarized by CMP and a pluralityof third dummy patterns 503 d made of the same material as the thirdwiring pattern 503 w.

Regions where the wiring patterns 501 w to 503 w are not formed in therespective layers 501 to 503 become dummy pattern formable regions 50Aand 50B and the dummy patterns 501 d to 503 d are arranged in therespective regions. The first dummy patterns 501 d are arranged to beclose-packed in the dummy pattern formable region 50A in the first layer501. A rectangular second dummy pattern 502 d is arranged in the dummypattern formable region 50A in the second layer 502 according to thefifth embodiment. The central axis of the second dummy pattern 502 d(shown by a dotted line) does not coincide with that of the first dummypattern 501 d (shown by a dashed line). That is, one rectangular seconddummy pattern 502 d is provided for two first dummy patterns 501 d. Therelationship between the two first dummy patterns 501 d and the onerectangular second dummy pattern 502 d is that a distance L₁ between thecentral axis of the first dummy pattern 501 d on the left side of thedotted line and the central axis of the second dummy pattern 502 d isequal to a distance L₂ between the central axis of the first dummypattern 501 d on the right side of the dotted line and the central axisof the second dummy pattern 502 d.

The third dummy patterns 503 d are arranged in the dummy patternformable region 50A so that central axes thereof coincide with those ofcorresponding ones of the first dummy patterns 501 d in a directionperpendicular to the semiconductor substrate as in the first to fourthembodiments.

Because the first dummy pattern 501 d is not formed in the dummy patternformable region 50B, the third dummy patterns 503 d are arranged to beclose-packed in this region. The rectangular second dummy pattern 502 dis arranged in the dummy pattern formable region 50B in the second layer502. The central axis of the dummy pattern 502 d (shown by a dottedline) does not coincide with that of the third dummy pattern 503 d(shown by a dashed line). That is, one rectangular-shaped second dummypattern 502 d is provided for two third dummy patterns 503 d. Therelationship between the two third dummy patterns 503 d and the onerectangular second dummy pattern 502 d is that a distance L₃ between thecentral axis of the first dummy pattern 503 d on the left side of thedotted line and the central axis of the second dummy pattern 502 d isequal to a distance L₄ between the central axis of the third dummypattern 503 d on the right side of the dotted line and the central axisof the second dummy pattern 502 d.

Because the predetermined relationship as described above is establishedbetween the dummy patterns of the upper and lower layers, the aboveconfiguration can suppress generation of moire due to dummy patterns atthe time of optically detecting defects. Thus, only minute particles anddefects can be correctly detected, and thus the yield can be improved.

The fifth embodiment represents a case that the width of the seconddummy pattern 502 d (a longer side in a planar configuration) is set tobe wider than twice the width of the first dummy pattern 501 d or thewidth of the third dummy pattern 503 d depending on design standards. Ifa second dummy pattern 502 dc is arranged in the dummy pattern formableregion 50A so that its central axis coincides with that of the firstdummy pattern 501 d like the first to fourth embodiments, the seconddummy pattern is arranged to approach one wiring 502 w as shown by along dashed line in FIG. 11A and a large area where the dummy pattern isnot formed remains on the side of the dummy pattern opposite to the sideapproaching the wiring, and this causes dishing and the like.Accordingly, when a dummy pattern which is twice, three times (andonwards) larger than a dummy pattern in one layer to be close-packedmust be provided in other layers, it is preferable to have theconfiguration of the fifth embodiment.

It is apparent that the present invention is not limited to the aboveembodiments, but may be modified and changed without departing from thescope and spirit of the invention.

While the first embodiment has described a case the plane sizes of alldummy patterns are the same and the second to fourth embodiments havedescribed cases that the plane sizes of the dummy patterns in therespective layers are different from each other, the present inventionis not limited thereto. For example, it is possible to have aconfiguration such that the plane sizes of the dummy patterns in atleast two layers of plural layers are the same and the plane sizes ofthe dummy patterns in other layers are different from each other.

It is basically preferable that the central axes of the dummy patternscorresponding to each other in the upper and lower layers coincide witheach other as described in the first to fourth embodiments. However,there is no problem when there are dummy patterns whose central axes donot coincide with each other, as far as minute particles and defects canbe correctly detected in defect inspections.

While a case that any of the layers should close-pack the dummy patternshas been described in the above embodiments, any of the layers does notneed to close-pack the dummy patterns as described first with referenceto FIG. 1. When any layer which close-packs the dummy patterns is notprovided, it suffices that the dummy patterns are close-packed in alayer with a high priority set in advance.

What is claimed is:
 1. A semiconductor device comprising: a first wiringstructure formed over a main surface of a substrate, the first wiringstructure including first and second wiring patterns disposed with afirst gap therebetween, first and second dummy patterns arranged in thefirst gap between the first and second wiring patterns and a firstinsulating layer covering the first and second wiring patterns and thefirst and second dummy patterns, the first and second dummy patternsbeing separated from each other; and a second wiring structure stackedwith the first wiring structure in a vertical direction with respect tothe main surface of the substrate, the second wiring structure includingthird and fourth wiring patterns disposed with a second gaptherebetween, a third dummy pattern arranged in the second gap betweenthe third and fourth wiring patterns and a second insulating layercovering the third and fourth wiring patterns and the third dummypattern; the third dummy pattern of the second wiring structure beingelongated in a horizontal direction with respect to the main surface ofthe substrate to overlap continuously both of the first and second dummypatterns of the first wiring structure.
 2. The device as claimed inclaim 1, wherein the second wiring structure is stacked over the firstwiring structure.
 3. The device as claimed in claim 2, furthercomprising a third wiring structure stacked over the second wiringstructure, the third wiring structure including fifth and sixth wiringpatterns disposed with a third gap therebetween, fourth and fifth dummypatterns arranged in the third gap between the fifth and sixth wiringpatterns and a third insulating layer covering the fifth and sixthwiring patterns and the fourth and fifth dummy patterns, the fourth andfifth dummy patterns of the third wiring structure being separated fromeach other and being vertically aligned in central axis with the firstand second dummy patterns of the first wiring structure, respectively.4. The device as claimed in claim 3, wherein the first, second and thirdgaps are different from one another.
 5. The device as claimed in claim2, wherein the first wiring structure further includes at least oneadditional dummy pattern that is arranged in the first gap and makes aline with the first and second dummy patterns, and the third dummypattern of the second wiring structure is free from overlapping the atleast one additional dummy pattern.
 6. The device as claimed in claim 3,wherein the first wiring structure further includes at least oneadditional dummy pattern arranged in the first gap, and a number ofdummy pattern arranged in the first gap of the first wiring structureare greater than that of dummy pattern arranged in the third gap of thethird wiring structure.
 7. The device as claimed in claim 2, wherein adistance between a center axis of the third dummy pattern and a centeraxis of the first dummy pattern is substantially equal to a distancebetween the center axis of the third dummy pattern and a center axis ofthe second dummy pattern.
 8. The device as claimed in claim 3, wherein adistance between a center axis of the third dummy pattern and a centeraxis of the first dummy pattern is substantially equal to a distancebetween the center axis of the third dummy pattern and a center axis ofthe second dummy pattern, and a distance between the center axis of thethird dummy pattern and a center axis of the fourth dummy pattern issubstantially equal to a distance between the center axis of the thirddummy pattern and a center axis of the fifth dummy pattern.
 9. Thedevice as claimed in claim 3, wherein the first dummy pattern of thefirst wiring structure is greater in area than the fourth dummy patternof the third wiring structure, and the second dummy pattern of the firstwiring structure is greater in area than the fifth dummy pattern of thethird wiring structure.
 10. The device as claimed in claim 1, whereinthe first wiring structure is stacked over the second wiring structure.11. The device as claimed in claim 10, wherein a distance between acenter axis of the third dummy pattern and a center axis of the firstdummy pattern is substantially equal to a distance between the centeraxis of the third dummy pattern and a center axis of the second dummypattern.
 12. The device as claimed in claim 10, further comprising athird wiring structure that includes a fifth wiring pattern, a fourthdummy pattern arranged adjacently to the fifth wiring pattern and athird insulating layer covering the fifth wiring pattern and the fourthdummy pattern, the second wiring structure being stacked over the thirdwiring structure such that the third dummy pattern of the second wiringstructure is positioned over the fifth wiring pattern of the thirdwiring structure.
 13. A semiconductor device comprising: a first levelwiring structure formed over a main surface of a substrate, the firstlevel wiring structure including first and second wiring patternsdisposed with a first gap therebetween, two or more first dummy patternsarranged in the first gap between the first and second wiring patternsand a first insulating layer covering the first and second wiringpatterns and the two or more first dummy patterns; a second level wiringstructure stacked over the first level wiring structure in a verticaldirection with respect to the main surface of the substrate, the secondlevel wiring structure including third and fourth wiring patternsdisposed with a second gap therebetween, at least one second dummypattern arranged in the second gap between the third and fourth wiringpatterns and a second insulating layer covering the third and fourthwiring patterns and the at least one second dummy pattern, the at leastone second dummy pattern being elongated in a horizontal direction withrespect to the main surface of the substrate to provide an elongateddummy pattern that continuously overlaps at least two of the two or morefirst dummy patterns of the first level wiring structure; and a thirdlevel wiring structure stacked over the second level wiring structure inthe vertical direction with respect to the main surface of thesubstrate, the third level wiring structure including fifth and sixthwiring patterns disposed with a third gap therebetween, at least twothird dummy patterns arranged in the third gap between the fifth andsixth wiring patterns and a third insulating layer covering the fifthand sixth wiring patterns and the at least two third dummy patterns, theat least two of the third dummy patterns being both located over theelongated dummy pattern and being vertically aligned in central axiswith the at least two of the two or more first dummy patterns,respectively.
 14. The device as claimed in claim 13, wherein the first,second and third gaps are different from each other.
 15. The device asclaimed in claim 13, wherein the first gap is greater than the secondgap, and the second gap is greater than the third gap.
 16. The device asclaimed in claim 13, wherein a distance between a center axis of the atleast one second dummy pattern and a center axis of one of the at leasttwo of the two or more first dummy patterns is substantially equal to adistance between the center axis of the at least one second dummypattern and a center axis of the other of the at least two of the two ormore first dummy patterns.
 17. The device as claimed in claim 16,wherein a distance between the center axis of the at least one seconddummy pattern and a center axis of one of the at least two third dummypatterns is substantially equal to a distance between the center axis ofthe at least one second dummy pattern and a center axis of the other ofthe at least two third dummy patterns.
 18. The device as claimed inclaim 13, wherein the second level wiring structure further includes afourth dummy pattern provided on an opposite side to the at least onesecond dummy pattern with respect to the third wiring pattern; andwherein the third level wiring structure further includes at least twofifth dummy patterns provided on an opposite side to the at least twothird dummy patterns with respect to the fifth wiring pattern, the atleast two fifth dummy patterns being both vertically located over thefourth dummy pattern of the second level wiring structure.
 19. Thedevice as claimed in claim 18, wherein a distance between a center axisof the fourth dummy pattern and a center axis of one of the at least twofifth dummy patterns is substantially equal to a distance between thecenter axis of the fourth dummy pattern and a center axis of the otherof the at least two fifth dummy patterns.
 20. The device as claimed inclaim 18, wherein the fourth dummy pattern is vertically located overthe first wiring pattern of the first level wiring structure.